Spatially Coupled Generalized LDPC Codes: Asymptotic Analysis and Finite Length Scaling

Notes: Finite-length Protograph-based Spatially Coupled LDPC Codes

The finite-length performance of multi-edge spatially coupled low-density parity-check (SC-LDPC) codes is analyzed over the binary erasure channel (BEC). Existing scaling laws are extended to arbitrary protograph base matrices including puncturing patterns and multiple edges between nodes. Compared to more involved rate-1/2 structures proposed to improve the threshold to minimum distance trade-...

Asymptotic and Finite-length Optimization of Ldpc Codes

This thesis addresses the problem of information transmission over noisy channels. In 1993, Berrou, Glavieux and Thitimajshima discovered Turbo-codes. These codes made it possible to achieve a very good performance at low decoding complexity. In hindsight, it was recognized that the underlying principle of using sparse graph codes in conjunction with message-passing decoding was the same as the...

Improving the Finite-Length Performance of Spatially Coupled LDPC Codes by Connecting Multiple Code Chains

In this paper, we analyze the finite-length performance of codes on graphs constructed by connecting spatially coupled low-density parity-check (SC-LDPC) code chains. Successive (peeling) decoding is considered for the binary erasure channel (BEC). The evolution of the undecoded portion of the bipartite graph remaining after each iteration is analyzed as a dynamical system. When connecting shor...

Finite-Length and Asymptotic Analysis and Design of LDPC Codes for Binary Erasure and Fading Channels

Memory Efficient Decoders using Spatially Coupled Quasi-Cyclic LDPC Codes

In this paper we propose the construction of Spatially Coupled Low-Density Parity-Check (SC-LDPC) codes using a Quasi-Cyclic (QC) algorithm. The QC based approach is optimized to obtain memory efficiency in storing the parity-check matrix in the decoders. A hardware model of the parity-check storage units has been designed for Xilinx FPGA to compare the logic and memory requirements for various...